Not Applicable.
Not Applicable.
1. Field of the Invention
The present invention relates to designing integrated circuits. More particularly, the present invention relates to determining transistor widths in integrated circuits.
2. Description of the Related Art
Integrated circuit (IC) design consists of a number of steps designed to aid in the complex task of design and verification. Typically, the design starts with a specification of the functional and performance characteristics of the IC. The IC is typically broken down into smaller units of the whole for design and testing.
Designers may write descriptions of the IC""s smaller units, or blocks, which are usable by various types of simulators. The blocks may be used to create a floor plan of the IC which shows the relative placement of the blocks. From the floor plan and descriptions, the designer finishes the circuit design. After the circuit design is finished, the layout of the circuit begins.
One of the areas of greatest effort for a designer is laying out the circuit in such a way as to meet timing constraints. Without a systematic approach, designers resort to continually simulating and modifying the design to achieve the timing constraints.
One way to assist designers in meeting the timing criteria is provided by a method of logical effort. The logical effort model is based on modeling the delay through a single logic element composed of metal-oxide-semiconductor (MOS) gate transistors. The model describes the delays caused by the capacitive load that the logic element drives and the topology of the logic element. As the load on a particular logic element increases, the delay of a signal through the logic element increases. However, the delay also depends on the topology of the logic element itself. For example, a typical transistor implementation of an inverter consists of an input going to the gates of two transistors, one n-type and one p-type. The drains of each transistor are connected together for the output and the sources are connected to power (the p-type) and ground (the n-type). In more complex logic elements, additional transistors may be connected in series or in parallel to power and ground. Transistors connected in series are less effective in driving a load as compared to similar transistors connected in parallel driving a similar load.
Delay through a logic element is composed of two components, a fixed parasitic delay and a stage effort delay. The stage effort delay, or effort delay, depends on the load on the logic element""s output and the particular size and topology of the gate. We can describe these two effects as the logical effort, which captures topological properties of the logic element, and the electrical effort, which characterizes the relative size of the load with respect to the width of the transistors in the logic element. The effort delay of a logic element comes from the product of the logical effort and the electrical effort.
The logical effort is independent of the width of the transistors in the circuit, while the electrical effort is the ratio of the load driven to the size of the transistors in the logic element. The electrical effort is defined as the capacitance that loads the output of the logic element divided by the capacitance presented by the input terminal of the logic element.
Logical effort is defined so that an inverter has a logical effort of one. Moreover, an inverter driving a copy of itself will have an electrical effort of one because the input and driven capacitance are equal. Accordingly, the effort delay through an inverter is 1. In general, the logical effort of a logic element describes how much worse it is at driving an output load than an inverter with the same capacitance presented at its inputs. Accordingly, the logical effort model illustrates how much more slowly it will drive a load than would an inverter. Another way to think of the logical effort is how much more input capacitance a logic element must present to deliver the same output current as an inverter.
The logical effort model is described more completely in Logical Effort: Designing Fast CMOS Circuits, by Ivan Sutherland, Bob Sproull, and David Harris, Morgan Kaufman Publishers, Inc. IBSN # 1-55860-557-6. This model is helpful to designers looking for speed by adjusting the stage efforts. It provides transistor sizes but only through laborious calculations.
The present invention provides a system and method for determining widths of transistors. After a circuit description including logic elements is created, each logic element is replaced with an associated sizing element to create a sizing model which retains the same wiring topology as the original circuit. The solution to the sizing model provides the transistor widths for the logic elements. The sizing model depends on a step-up value and a logical effort value for each input of each logic element. The calculations on the sizing model may be accomplished by analog circuit simulation methods, Gaussian elimination methods, or approximation methods.
According to the invention, the sizing element used for each logic element delivers current at each logic element input and receives current at each logic element output. Thus, the logic element input becomes a current source in the sizing element and the logic element output becomes a current sink in the sizing element. The input of the logic element in the sizing element becomes a current source providing an indication of how much current would be required to drive the logic element input. Furthermore, the current delivered by this source is proportional to current values received at the sizing element sink.
In one aspect of the invention each output of the logic element is replaced with a device that accepts a current. The device may be a resistor or tunable resistor. In another aspect, the resistor has a resistance equal to an inverse of the step-up value. The voltage appearing across the resistor determines the logic element sizing. The current received at the sizing element sink is the sum of all of the currents from source terminals of the sizing elements of other logic elements connected to the particular sizing element. The received current is indicative of the total load driven by the logic element output.
The current delivered by the sizing element source at the circuit element""s input is proportional to a logical effort of that input of the circuit element. In another aspect the input of the circuit element is replaced with a sizing element that produces a current proportional to a required charge of the input of the circuit element. The required charge is proportional to a size of the capacitance presented by the input to the circuit element.
In still another aspect of the invention, the sizing element output includes a current generating device adapted to generate a current equal to a logical effort value multiplied by the voltage appearing at the current sinking device. The logical effort value can be input by various means or be fixed.
In yet another aspect, the current produced by the sizing element is equal to the current appearing at the sizing element input multiplied by the logical effort of the input to the circuit element, that result divided by the step-up for the circuit element.
In another aspect of the invention, a system is provided whereby a plurality of sizing elements, each corresponding to a particular logic element, replaces its logic circuit element. The circuit elements have inputs and an output which are replaced by sources and drains, respectively, of the module primitives. A support is provided upon which to place the module primitives. Connectors are provided for connecting module primitives on the support.
In one aspect, each module primitive has a current source connected to the module primitive output, the output of the current source being proportional to a logical effort of the logic element input.
If the circuit element has an output, then the output is replaced by a module primitive drain corresponding to the circuit element output and a resistor connected between the module primitive drain terminal and ground. The resistor may be tunable.
In another aspect, the module primitive further includes a logical effort input adapted to receive a value of the logical effort for each input. In still another aspect of the invention, the circuit primitive has a step-up value that may be fixed or variable.
The system also includes an indicator adapted to indicate the circuit element size.
In another aspect of the invention, a method is provided for determining a logic element""s size by computing the driven load incurred by the driving logic element and dividing the driven load by a step-up value to determine the driving logic element size. For each driven logic element that the driving logic element drives, a respective logic element load is calculated and summed to determine the driven load. To calculate the respective logic element load, a driven logic element""s size is multiplied by the logical effort of the driven input of the logic element.
In one aspect the resultant size is the larger of a minimum circuit element size and the result of calculating the driving logic element size.
In another aspect of the invention a method of computing logic element sizes is provided that computes for each driving logic element in a circuit design, a respective driven load incurred by each driving logic element based on a respective step-up value and then dividing the respective driven load by the respective step-up value to determine the respective logic element size. The respective driven load is determined by calculating, for each driven logic element, a respective logic element load and summing, for each driven logic element, the respective logic element loads to determine the respective driven load. The respective logic element load is calculated by multiplying a driven logic element""s size by a logical effort of the driven input of the logic element.
In another aspect of the invention the logic element size is the larger of a minimum logic element size and the result of the dividing step for each driving logic element.